In conventional multiprocessor (MP) systems, multiple processors have access to a common shared memory. To improve the performance of these systems, the storage models for ordering of storage accesses is weakly consistent. Weakly consistent means that the order in which accesses are performed by the processor, the ordering in which these accesses are performed on the processor bus, the order in which accesses are performed with respect to another processor or mechanism, and the order in which these accesses are performed in storage may all be different.
The weakly consistent storage model places on a software program the responsibility to ensure the ordering of accesses to storage that is shared among two or more processors and/or mechanisms. In a conventional symmetric multiprocessor (SMP), several means are provided to allow a software program to enforce ordering of storage access to shared memory. For example, on the PowerPC®, a plurality of memory barrier instructions are provided, such as “SYNC” (also sometimes referred to as “heavy-weight SYNC”), “lightweight SYNC,” and “EIEIO” (Enforce In-order Execution of I/O). Generally, the SYNC instruction creates a memory barrier. That is, on a given processor, any load or store instructions ahead of the SYNC instruction in the program sequence must complete with respect to all other processors and mechanisms, before any instruction after the SYNC instruction can be executed.
A lightweight SYNC creates a memory barrier that provides the same ordering function as the SYNC instruction, except that a load caused by an instruction following the lightweight SYNC may be performed before a store caused by an instruction that precedes the lightweight SYNC, and the ordering does not apply to accesses to I/O memory (memory-mapped I/O). The EIEIO instruction creates a memory barrier that provides the same ordering function as the SYNC instruction except that ordering applies to accesses to I/O memory. The EIEIO also orders stores.
In a conventional MP system, execution of memory barrier instructions is limited to tightly coupled processors, which places an additional workload on the control processors (i.e., processing units (PUs)) to manage other non-symmetric processors and/or devices within a heterogeneous MP system. In some cases, this limitation can also limit the ability of a non-symmetrical processor to manage system resources since the storage ordering cannot be controlled.
Therefore, there is a need for a method and/or system for providing memory barrier instructions that addresses at least some of the problems and disadvantages associated with conventional systems and methods.